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  1. Dual-band antenna for passive RFID tags
  2. Compact and high performance filters for mobile communication
  3. Design and FPGA implementation of digit-serial FIR filters
  4. Advanced filter bank based ADC for software defined radio applications
  5. Call line identity device with integrated sound output
  6. PLL based frequency synthesizer implemented with an active inductor oscillator
  7. A radio-frequency mosfet driver
  8. A design of a frequency hopping spread spectrum transceiver for CDMA2000 systems
  9. Optimised asynchronous timing for superconductive digital circuits

Dual-Band antenna for passive RFID tags by C.A. Diugwu, J.C. Batchelor, R.J. Langley and M. Fogg.
Abstract: This paper presents an overview of recent state of the art in antenna technology for passive RFID tags used for fi eld and asset tracking. Improved detection ranges have been realised utilising planar antenna technology with the benefi ts of low-cost, ease of manufacture and low-profi le. These are offset by the disadvantages of narrow bandwidth and low power capacity. Improvements in passive RFID tag antenna design operating at the ultra high frequency (UHF) and microwave frequency bands are detailed and discussed. Numerical results are calculated using fi nite integral techniques (FIT) of the CST microwave studio.
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Compact and high performance filters for mobile communication by J.M. Chuma, D. Mirshekar, S. Masupe and K. Kepaletswe
Abstract: In the marketplace, where price and performance requirements are challenging to meet, size has become an extremely important factor for cellular base stations. In current mobile communications bands, air-fi lled fi lters, which tend to be bulky, are used in base stations. In this contribution, the alternative use of a dielectric loaded combline fi lter is proposed in order to reduce the size of fi lters, and enhance their performance. An eighthorder canonical combline fi lter is designed with this in mind, for which measured results show improved performance.
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Design and FPGA implementation of digit-serial FIR filters by D.S. Dawoud and S. Masupa
Abstract: In this paper the design of a digital-serial N-tap FIR fi lter with programmable coefficients is presented. The design considers the general case of W-bit sample word and mbit coefficient word. The processing of the data within the fi lter takes place with full precision. The output data is truncated to W bits. The design introduced the new digit-serial multiplier that guarantees minimum processing time and reduces the hardware requirements. Signamplitude representation for the coefficients and two’s complement for the input samples simplified the circuit configuration and allows the use of a single common two’s complement circuit for all the fi lter sections. A 100-tap, 8-bit word length version fi lter is implemented using an ALTERA FPGA device. The filter can be used in real-time processing with sample rates ranging from 7.5 to 22 MHz
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Advanced filter bank based ADC for sorftware defined radio applications by D.S. Dawoud and S.E. Phakathi
Abstract. In this paper, the recent used concepts for the design high resolution wide bandwidth analogue-to-digital converters (ADCs) are presented. Practical issues regarding the realization of time-interleaved oversampling converters are discussed. The use of hybrid filter banks for the realizations is also considered. The possibility of using frequency-division multiplexing (FDM) together with time-division multiplexing to build DAC suitable for software radio applications is considered.
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Call line Identity device with integrated sound output by M.A. Beukes and B.M. Lacquet
Abstract: It has become obvious that technology, in some cases, exceed our humanity. The dilemma for the visually impaired is that they cannot benefit from electronic devices with Liquid Crystal Display (LCD) technology. Most electronic devices convey information to the user by displaying it on these LCD’s. Adapted products exist, but because no market for these products have been established, relatively small numbers are imported. Therefore a few useful products are available at an affordable cost. We present the design and construction of a talking call line identification unit with integrated sound output to be used on Telkom lines. This unit incorporates audio and visual input/output of all on-board functions, thus visually impaired user’s can navigate the unit settings, assisted by pre-recorded voice prompts and big input buttons. A graphical LCD completes the unit, as it could still be used by the un-impaired. The re-production of a human voice is accomplished by pre-recording on a solid-state ISD (Information Storage Device) capable of recording eight minutes of voice data. This enables the unit to announce the incoming caller’s number or an associated recording of the caller’s name. This device comes as a great benefit for not only the visually impaired but normal user’s of telephones as well.
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PLL based frequency synthesizer implemented with an active inductor oscillator by S. Sinha and M. du Plessis
Abstract: High costs, bulkiness, and larger power consumption makes transceiver integration and miniaturization a desired option to discretely implemented transceivers. Furthermore, a frequency synthesizer forms an important part of high-frequency transceivers. In this paper, the design of a fully-integrated dual loop frequency synthesizer is detailed. Previously, frequency synthesizers have already been implemented using CMOS technology. The synthesizer discussed in this paper deploys a dual loop architecture with a high-frequency LC voltage controlled oscillator (VCO) forming part of one of the loops. As opposed to previous architectures, the synthesizer discussed in this paper utilises an active-inductor LC VCO as opposed to a passive-inductor LC VCO deployed in earlier synthesizer implementations. Amongst others, an important advantage of this implementation is the higher quality, Q-factor of the active inductor at the trade-off of increased noise and power dissipation. The synthesizer generates signals in the microwave frequency (2.4-2.5 GHz) range with a 1 MHz resolution. Using the 0.35 μm BiCMOS process, simulations showed a phase noise of –117 dBc/Hz at an offset of 1 MHz and reference sidebands at -80 dBc, both these parameters with respect to a 2.45 GHz carrier.
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A radio-frequency mosfet driver by A.J. Swart, H.C. vZ. Pienaar and M.J. Case
Abstract: High power MOSFETS have become synonymous with power electronics applications. The ability of high power MOSFETS to act as a switch makes it the ideal switching device, where maximum voltage and zero current must occur when the device is open. When closed, the MOSFET must allow maximum current to fl ow with zero voltage across it [1] [2] [3]. This technique of switching between maximum and zero voltage across the high power MOSFET is readily achieved at frequencies below 1 MHz. Raising the frequency to within the radio-frequency range presents numerous challenges, as high power MOSFETS tend to have a frequency cut-off point. This paper attempts to address the switching habits and limits of high power MOSFETS within the radio-frequency range by means of computer simulation and experimental verifi cation.
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A design of a frequency hopping spread spectrum tranciever for CDMA2000 systems by H.R. Swanepoel and S. Sinha
Abstract: This paper presents an integrated frequency hopped transceiver based on a subset of the cdma2000 network specifications. The circuit consists of a phase locked loop (PLL) that generates the hopping carriers, local oscillators (LOs) that generate GHz range carrier frequencies, and a series of mixers. It accepts input data in frequency shift keyed (FSK) format, and also outputs received data in FSK format.
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Optomised asynchronous timing for superconductive digital circuits by H.R. Gerber, C.J. Fourie and W.J. Perold
Abstract: Rapid Single Flux Quantum (RSFQ) logic is a digital circuit technology that in recent years has presented itself as an alternative to semiconductors in the application of ultra high speed, very low power applications. The optimal timing of digital circuits operating at hundreds of Gigahertz is still a complex problem for both RSFQ and semiconductor technologies. The fact that most RSFQ gates require a clock signal to function makes this even more complex. Various RSFQ timing schemes have been adapted from semiconductor design methodologies, and some have been designed specifically for RSFQ. Currently, synchronous clocking schemes outperform other schemes, but with the scale of RSFQ circuits ever increasing, the proper use of timing schemes are becoming more crucial. This paper describes a new asynchronous self-timing scheme where the details of clock distribution and clocking are built into the logic gates. Tests were done on the newly developed asynchronous logic gates and a asynchronous full adder was implemented and tested.
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