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1. New Generation Three-Phase Rectifier
2. Symbol Error Probability for Generalized Selection Combining Reception of M-QAM
3. Mathematical Modelling of the LC-Ladder and Capacitive Shunt-Shunt Feedback LNA Topology
4. Design Approach to CMOS Based Class-E and Class-F Power Amplifiers

New Generation Three-Phase Rectifier by W. Phipps, R.T. Harris and A.G. Roberts
Abstract: This paper describes an investigation into the development of a new generation of three-phase rectifier, used to power telecommunications equipment. Traditionally, the topology used is a single-phase two-stage design, with a boost converter at the input to the first stage and an isolated dc-dc converter making up the second stage. The boost converter provides power factor correction which is necessary in order to comply with the IEC1000-3-2 standard. The dc-dc stage provides isolation, as well as the fast feedback necessary to regulate the output voltage ripple. This is necessary in order to comply with the psophometric noise standard ITU-T0.41. A two-stage design however, results in a cascade effect contributing to the total power losses. A new rectifier is introduced that can satisfy the required telecommunication industry standards, whilst also having only a single-stage design. This paper discusses the principles of operation and the performance characteristics of the new generation three-phase rectifier.
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Symbol Error Probability for Generalized Selection Combining Reception of M-QAM by H. Xu
Abstract: In this paper, symbol error probability (SEP) for generalized selection combining (GSC) reception of M-ary quadrature amplitude modulation (M-QAM) signals in a block frequency-flat Rayleigh fading channel is considered. The paper presents a closed-form approximate SEP expression for GSC reception of M-QAM signals in the fading channel. The SEP expression is explicit and simulation results validate that it is very accurate.
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Mathematical Modelling of the LC-Ladder and Capacitive Shunt-Shunt Feedback LNA Topology by M. Weststrate and S. Sinha
Abstract: In this paper a new low noise amplifier configuration is proposed to achieve wideband operation. This configuration consists of an LC-ladder filter and a common-emitter stage employing shunt-shunt capacitive feedback to realize wideband matching. Design equations for this configuration are derived, as well as equations for the important performance measures namely noise figure, gain and IIP3. The results of a design for achieving typical low noise amplifier specifications in the ultra-wideband are calculated from these equations and plotted. Without any optimization S11 of less than -10 dB over the entire frequency band and a minimum noise figure of 2.7 dB are predicted when achieving S21 of 20 dB. These results indicate that very good performance can be attained through the use of this technique. Simulations were also done to verify the calculated results.
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Design Approach to CMOS Based Class-E and Class-F Power Amplifiers by M. Bozanic and S. Sinha
Abstract: This paper presents the design flow for an integrated power amplifier. The flow is presented as a software routine. For a given set of amplifier specifications and CMOS process parameters, the routine computes the passive component values for a Class-E or Class-F based power amplifier. The routine includes the matching network for standard impedance loads. The routine also provides its user with a spiral inductor search algorithm, which can be used to generate layouts of inductors with Q-factors optimised at a desired frequency. For a typical power amplifier design case where several amplifiers are designed for application over different channels, the routine presented in this paper contributes by streamlining the design flow. The operation of the software routine was demonstrated by simulations in Austriamicrosystems 0.35 µm single-supply process for a 14 dBm, 2.4 GHz power amplifier design.
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